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| ZMD31050 Advanced Differential Sensor Signal Conditioner Datasheet Features * * * * * * * * * * * * Digital compensation of sensor offset, sensitivity, temperature drift and non-linearity Accommodates nearly all bridge sensor types (signal spans from 1 up to 275mV/V processable) Digital one-shot calibration: quick and precise Selectable compensation temperature T1 source: bridge, thermistor, internal diode or external diode Output options: voltage (0...5V), current (4...20mA), PWM, I2C, SPI, ZACwireTM (one-wireinterface), alarm Adjustable output resolution (up to 15 bits) versus sampling rate (up to 3.9kHz) Selectable bridge excitation: ratiometric voltage, constant voltage or constant current Input channel for separate temperature sensor Sensor connection and common mode check (Sensor aging detection) operation temperature, depending on product version, up to -40...+125 (-40...+150 derated) C C Supply voltage +2.7V...+5.5V Available in SSOP16 or as die PRELIMINARY Brief Description ZMD31050 is a CMOS integrated circuit for highlyaccurate amplification and sensor-specific correction of bridge sensor signals. The device provides digital compensation of sensor offset, sensitivity, temperature drift and non-linearity by a 16-bit RISC micro controller running a correction algorithm with correction coefficients stored in non-volatile EEPROM. The ZMD31050 accommodates virtually any bridge sensor (e.g. piezo-resistive, ceramic-thickfilm or steel membrane based). In addition, the IC can interface a separate temperature sensor. The bi-directional digital interfaces (I2C, SPI, ZACwireTM) can be used for a simple PC-controlled one-shot calibration procedure, in order to program a set of calibration coefficients into an on-chip EEPROM. Thus a specific sensor and a ZMD31050 are mated digitally: fast, precise and without the cost overhead associated with laser trimming, or mechanical potentiometer methods. Application kit available (SSOP16 samples, calibration PCB, calibration software, technical documentation) Support for industrial mass calibration available Quick circuit customization possible for large production volumes Benefits * * * No external trimming components required PC-controlled configuration and calibration via digital bus interface - simple, low cost High accuracy (0.1% FSO @ -25...85 0.25% C; FSO @ -40...125 C) Application Circuit (Examples) VDDA = 5 V VSUPP 100 nF 100 nF 100 nF 100 nF +7...+40 V VSUPP 15 nF Re (120 ) Rsens(50 ) Fig.1: Ratiometric measurement with voltage output, temperature compensation via external diode Fig.2: Two-wire-(4 to 20) mA configuration [(7 to 40) V], temperature compensation via internal diode Refer also chapter 2 for additional application circuits and details Copyright (c) 2005, ZMD AG, Rev. 0.95, 2005-09-16 1/20 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The Information furnished in this publication is preliminary and subject to changes without notice. ZMD31050 Advanced Differential Sensor Signal Conditioner Datasheet PRELIMINARY Contents 1. CIRCUIT DESCRIPTION ........................................................................................................... 3 1.1 SIGNAL FLOW ........................................................................................................................... 3 1.2 APPLICATION MODES ................................................................................................................ 4 1.3 ANALOG FRONT END (AFE)....................................................................................................... 5 1.3.1. Programmable Gain Amplifier........................................................................................... 5 1.3.2. Analog Sensor Offset Compensation - Analog Zero Point Shift (AZS).............................. 5 1.3.3. Measurement Cycle realized by Multiplexer...................................................................... 6 1.3.4. Analog-to-Digital Converter .............................................................................................. 7 1.4 SYSTEM CONTROL .................................................................................................................... 8 1.5 OUTPUT STAGE ........................................................................................................................ 9 1.5.1. Analog Output ................................................................................................................ 10 1.5.2. Comparator Module (ALARM Output)............................................................................. 10 1.5.3. Serial Digital Interface .................................................................................................... 10 1.6 VOLTAGE REGULATOR ............................................................................................................ 11 1.7 WATCHDOG AND ERROR DETECTION ....................................................................................... 11 2. 3. 4. 5. 5.1 5.2 5.3 5.4 5.5 6. 7. 8. 9. APPLICATION CIRCUIT EXAMPLES ..................................................................................... 12 ESD/LATCH-UP-PROTECTION .............................................................................................. 13 PIN CONFIGURATION AND PACKAGE ................................................................................. 13 IC CHARACTERISTICS........................................................................................................... 14 ABSOLUTE MAXIMUM RATINGS................................................................................................. 14 OPERATING CONDITIONS (VOLTAGES RELATED TO VSS) ....................................................... 14 BUILD IN CHARACTERISTICS .................................................................................................... 15 ELECTRICAL PARAMETERS (VOLTAGES RELATED TO VSS) .................................................... 17 INTERFACE CHARACTERISTICS................................................................................................. 18 TEST........................................................................................................................................ 19 RELIABILITY ........................................................................................................................... 19 CUSTOMIZATION ................................................................................................................... 19 RELATED DOCUMENTS......................................................................................................... 19 Copyright (c) 2005, ZMD AG, Rev. 0.95, 2005-09-16 2/20 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The Information furnished in this publication is preliminary and subject to changes without notice. ZMD31050 Advanced Differential Sensor Signal Conditioner Datasheet PRELIMINARY 1. 1.1 CIRCUIT DESCRIPTION Signal Flow Fig.3: Block diagram of ZMD31050 PGA MUX ADC CMC DAC FIO1 FIO2 PCOMP EEPROM TS ROM PWM programmable gain amplifier multiplexer analog-to-digital converter calibration microcontroller digital-to-analog converter flexible I/O 1: analog out (voltage/current), PWM2, ZACwireTM (one-wire-interface) flexible I/O 2: PWM1, SPI data out, SPI slave select, Alarm1, Alarm2SIF serial interface: I2C data I/O, SPI data in, clock programmable comparator for calibration parameters and configuration on-chip temperature sensor (pn-junction) for correction formula and -algorithm PWM module The ZMD31050's signal path is partly analog (blue) and partly digital (red). The analog part is realized differential - this means internal is the differential bridge sensor signal also handled via two signal lines, which are rejected symmetrically around a common mode potential (analog ground = VDDA/2). Consequently it is possible to amplify positive and negative input signals, which are located in the common mode range of the signal input. The differential signal from the bridge sensor is pre-amplified by the programmable gain amplifier (PGA). The Multiplexer (MUX) transmits the signals from bridge sensor, external diode or separate temperature sensor to the ADC in a certain sequence (instead of the temperature diode the internal pn-junction (TS) can be used optionally). Afterwards the ADC converts these signals into digital values. Copyright (c) 2005, ZMD AG, Rev. 0.95, 2005-09-16 3/20 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The Information furnished in this publication is preliminary and subject to changes without notice. ZMD31050 Advanced Differential Sensor Signal Conditioner Datasheet PRELIMINARY The digital signal correction takes place in the calibration micro-controller (CMC). It is based on a special correction formula located in the ROM and on sensor-specific coefficients (stored into the EEPROM during calibration). Dependent on the programmed output configuration the corrected sensor signal is output as analog value, as PWM signal or in digital format (SPI, I2C, ZACwireTM ). The output signal is provided at 2 flexible I/O modules (FIO) and at the serial interface (SIF). The configuration data and the correction parameters can be programmed into the EEPROM via the digital interfaces. The modular circuit concept enables fast custom designs varying these blocks and, as a result, functionality and die size. 1.2 Application Modes For each application a configuration set has to be established (generally prior to calibration) by programming the on-chip EEPROM regarding to the following modes: - - - - - - - - - - Sensor channel Sensor mode: ratiometric voltage or current supply mode. Input range: The gain of the analog front end has to be chosen with respect to the maximum sensor signal span and to this has also adjusted the zero point of the ADC Additional offset compensation: The extended analog offset compensation has to be enabled if required, e.g. if the sensor offset voltage is near to or larger than the sensor span. Resolution/response time: The A/D converter has to be configured for resolution and converting scheme (first or second order). These settings influence the sampling rate, signal integration time and this way the noise immunity. The Sample Order influences the response time too. Ability to invert the sensor bridge inputs Analog output Choice of output method (voltage value, current loop, PWM) for output register 1. Optional choice of additional output register 2: PWM via IO1 or alarm out module via IO1/2. Digital communication: The preferred protocol and its parameter have to be set. Temperature The temperature measure source for the temperature correction has to be chosen. The temperature measure source T1 sensor type for the temperature correction has to be chosen (only T1 is usable for correction!!!) Optional: the temperature measure channel as the second output has to be chosen. Supply voltage : For non-ratiometric output the voltage regulation has to be configured. Note: Not all possible combinations of settings are allowed (see section 1.5). The calibration procedure must include - the set of coefficients of calibration calculation and, depending on configuration, - the adjustment of the extended offset compensation, - the zero compensation of temperature measurement, - the adjustment of the bridge current and, if necessary, - the set of thresholds and delays for the alarms and the reference voltage. Copyright (c) 2005, ZMD AG, Rev. 0.95, 2005-09-16 4/20 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The Information furnished in this publication is preliminary and subject to changes without notice. ZMD31050 Advanced Differential Sensor Signal Conditioner Datasheet 1.3 Analog Front End (AFE) PRELIMINARY The analog front end consists of the programmable gain amplifier (PGA), the multiplexer (MUX) and the analog-to-digital converter (ADC). 1.3.1. Programmable Gain Amplifier The following tables show the adjustable gains, the processable sensor signal spans and the allowed common mode range. No. PGA Gain aIN Gain Amp1 Gain Amp2 Gain Amp3 Max. span VIN_SP in mV/V Input range VIN_CM in % VDDA 43 - 57 40 - 59 43 - 57 40 - 59 38 - 62 40 - 59 38 - 62 40 - 59 38 - 62 43 - 57 40 - 59 38 - 62 21 - 76 mode ranges 1 420 30 7 2 280 30 4,66 3 210 15 7 4 140 15 4,66 5 105 15 3,5 6 70 7,5 4,66 7 52,5 7,5 3,5 8 35 3,75 4,66 9 26,3 3,75 3,5 10 14 1 7 11 9,3 1 4,66 12 7 1 3,5 13 2,8 1 1,4 Table 1: Adjustable gains, resulting 1.3.2. * * 2 2 2 3 2 4 2 6 2 8 2 12 2 16 2 24 2 32 2 50 2 80 2 100 2 280 sensor signal spans and common Analog Sensor Offset Compensation - Analog Zero Point Shift (AZS) The ZMD31050 supports two methods of sensor offset cancellation (zero shift): digital offset correction analog cancellation for large offset values (up to approx 300% of span) Digital sensor offset correction will be processed at the digital signal correction/conditioning by the CMC. Analog sensor offset pre-compensation will be needed for compensation of large offset values, which would be overdrive the analog signal path by uncompensated gaining. For analog sensor offset pre-compensation a compensation voltage will be added in the analog pre-gaining signal path (coarse offset removal). The analog offset compensation in the AFE can be adjusted by 6 EEPROM bits. It allows an Analog Zero Point Shift up to 300% of the processable signal span. The zero point shift of the temperature measurements can also be adjusted by 6 EEPROM bits (ZAZS= -25...+25) and is calculated by: VAZS / VDDBR= k * ZAZS / ( 20 * aIN) Bridge in voltage mode, refer "ZMD31050 Functional description" for usable input signal/common mode range at bridge in current mode Copyright (c) 2005, ZMD AG, Rev. 0.95, 2005-09-16 5/20 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The Information furnished in this publication is preliminary and subject to changes without notice. ZMD31050 Advanced Differential Sensor Signal Conditioner Datasheet PRELIMINARY PGA gain aIN Max. span VIN_SP in mV/V Calculation factor k Offset shift per step in % full span 15% 9% 15% 9% 6% 9% 6% 9% 6% 15% 9% 6% 1% Approx. maximum offset shift in mV/V +/- 9 +/- 8 +/- 18 +/- 18 +/- 15 +/- 33 +/- 44 +/-66 +/- 87 +/- 270 +/- 250 +/- 225 +/- 90 420 280 210 140 105 70 52,5 35 26,3 14 9,3 7 2,8 2 3 4 6 8 12 16 24 32 50 80 100 280 3,0 1,833 3,0 1,833 1,25 1,833 1,25 1,833 1,25 3,0 1,833 1,25 0,2 Approx. maximum shift in [% VIN_SP] (@ 25) 450 266 450 300 187 275 275 275 272 540 312 225 32 Table 2: Analog Zero Point Shift Ranges 1.3.3. Measurement Cycle realized by Multiplexer The Multiplexer selects, depending on EEPROM settings, the following inputs in a certain sequence. Bridge temperature signal measured by external diode Bridge temperature signal measured by internal pn-junction Bridge temperature signal measured by bridge resistors Separate temperature signal measured by external thermistor Internal offset of the input channel measured by input short circuiting Pre-amplified bridge sensor signal Start routine The complete measurement cycle is controlled by the CMC. The cycle diagram at the right shows its principle structure. The EEPROM adjustable parameters are: Pressure measurement count, n=<1,2,4,8,16,32,64,128> Enable temperature measurement 2, e2=<0,1> n 1 n 1 n 1 n * e2 e2 n * e2 e2 * * Pressure measurement Temp 1 auto zero Pressure measurement Temp 1 measurement Pressure measurement Pressure auto zero Pressure measurement Temp 2 auto zero Pressure measurement Temp 2 measurement After Power ON the start routine is called. It contains the pressure and auto zero measurement. When enabled it measures the temperature and its auto zeros. Fig. 4: Measurement cycle ZMD31050 Copyright (c) 2005, ZMD AG, Rev. 0.95, 2005-09-16 6/20 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The Information furnished in this publication is preliminary and subject to changes without notice. ZMD31050 Advanced Differential Sensor Signal Conditioner Datasheet 1.3.4. Analog-to-Digital Converter PRELIMINARY The ADC is a charge balancing converter in full differential switched capacitor technique. It can be used as first or second order converter: In the first order mode it is inherently monotone and insensitive against short and long term instability of the clock frequency. The conversion cycle time depends on the desired resolution and can be roughly calculated by: tCYC_1 = 2 rADC s The available ADC-resolutions are rADC = <9,10,11,12,13,14,15>. In the second order mode two conversions are stacked with the advantage of much shorter conversion cycle time and the drawback of a lower noise immunity caused by the shorter signal integration period. The conversion cycle time at this mode is roughly calculated by: tCYC_2 = 2 (rADC +3)/2 s The available ADC-resolutions are rADC = <10,11,12,13,14,15>. The result of the AD conversion is a relative counter result corresponding to the following equation: ZADC = 2 ZADC: VADC_DIFF: VADC_REF: RSADC: rADC * [(VADC_DIFF /VADC_REF) + (1 - RSADC)] number of counts (result of the conversion) differential input voltage of ADC (= aIN * VIN_DIFF) reference voltage of ADC (= VDDBR at ratiometric measurement) digital ADC Range Shift (RSADC = 15/16, 7/8, 3/4, 1/2, controlled by the EEPROM content) With the RSADC value a sensor input signal can be shifted in the optimal input range of the ADC. Note: The AD conversion time is only a part of a whole sample cycle. Thus the sample rate is lower then the AD conversion rate. ADC Order OADC 1 1 1 1 1 1 1 2 2 2 2 2 2 rADC* Bit 9 10 11 12 13 14 15 10 11 12 13 14 15 Maximum Output Resolution Digital-OUT Analog-OUT rPWM Bit Bit Bit 9 10 11 12 13 14 15 10 11 12 13 14 15 9 10 11 11 11 11 11 10 11 11 11 11 11 9 10 11 12 12 12 12 10 11 12 12 12 12 Sample Rate fCON fCLK=2MHz fCLK =2.25MHz Hz Hz 1302 781 434 230 115 59 30 3906 3906 3906 1953 1953 977 1465 879 488 259 129 67 34 4395 4395 4395 2197 2197 1099 Table 3: Output resolution versus sample rate *ADC Resolution should be 1 or 2 Bits higher then applied Output Resolution Copyright (c) 2005, ZMD AG, Rev. 0.95, 2005-09-16 7/20 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The Information furnished in this publication is preliminary and subject to changes without notice. ZMD31050 Advanced Differential Sensor Signal Conditioner Datasheet 1.4 System Control PRELIMINARY The system control has the following features: Control of the I/O relations and of the measurement cycle regarding to the EEPROM-stored configuration data 16 bit correction calculation for each measurement signal using the EEPROM stored calibration coefficients and ROM-based algorithms Started by internal POC, internal clock - generator or external clock For safety improvement the EEPROM data are proved with a signature within initialization procedure, the registers of the CMC are steadily observed with a parity check. Once an error is detected, the error flag of the CMC is set and the outputs are driven to a diagnostic value Note: The conditioning includes up to third order sensor input correction. The available adjustment ranges depend on the specific calibration parameters, a detailed description will be issued later. To give a rough idea: Offset compensation and linear correction are only limited by the loose of resolution it will cause, the second order correction is possible up to about 30% full scale difference to straight line, third order up to about 20% (ADC resolution = 13bit). The temperature calibration includes first and second order correction and should be fairly sufficient in all relevant cases. ADC resolution influences also calibration possibilities - 1 bit more resolution reduces calibration range by approximately 50%. Copyright (c) 2005, ZMD AG, Rev. 0.95, 2005-09-16 8/20 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The Information furnished in this publication is preliminary and subject to changes without notice. ZMD31050 Advanced Differential Sensor Signal Conditioner Datasheet 1.5 Output Stage Used serial IF No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 IC X X X X X X X X X X X X X X X X X X X X Analog Analog Analog Analog Analog Analog PWM2 PWM2 PWM2 PWM2 PWM2 PWM2 ALARM1 PWM1 PWM1 Data out Data out ALARM1 Data out PWM1 Analog Analog Data out Data out ALARM1 Data out PWM1 Data out Data out ALARM1 Data out PWM1 ALARM2 Slave select Slave select Slave select Slave select Slave select Slave select Slave select Slave select Slave select ALARM1 ALARM2 ALARM2 ALARM1 PWM1 PWM1 ALARM2 ALARM1 ALARM2 ALARM2 ALARM1 PWM1 PWM1 ALARM2 ALARM1 ALARM2 ALARM2 2 PRELIMINARY Used I/O pins OUT IO1 IO2 SDA Data I/O Data I/O Data I/O Data I/O Data I/O Data I/O Data I/O Data I/O Data I/O Data I/O Data I/O Data I/O Data I/O Data I/O Data I/O Data I/O Data I/O Data I/O Data in Data in Data in Data in Data in Data in Data in Data in Data in - SPI The ZMD31050 provides the following I/O pins: OUT, IO1, IO2 and SDA. Via these pins the following signal formats can be output: Analog (voltage/current), PWM, Data (SPI/I2C), Alarm. The following values can be provided at the O/I pins: bridge sensor signal, temperature signal 1, temperature signal 2, alarm. Note: The Alarm signal only refers to the bridge sensor signal, but never to a temperature signal. Due to the necessary pin sharing there are restrictions to the possible combinations of outputs and interface connections. The table beside gives an overview about possible combinations. Note: In the SPI mode the pin IO2 is used as Slave select. Thus no Alarm 2 can be output in this mode. 21 X 22 23 X X 24 X Analog 25 26 X X PWM2 PWM2 27 X PWM2 Table 4: Output configurations overview Copyright (c) 2005, ZMD AG, Rev. 0.95, 2005-09-16 9/20 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The Information furnished in this publication is preliminary and subject to changes without notice. ZMD31050 Advanced Differential Sensor Signal Conditioner Datasheet PRELIMINARY 1.5.1. Analog Output For the analog output 3 registers of 15 bit depth are available, which can store the actual pressure and the results of temperature measurement 1 and 2. Each register can be independently switched to one of two output slots connected to the Pin OUT and IO1 respectively. In these output slots different output modules are available according to the following table: Output slot: OUT Voltage x PWM x Table 5: Analog output configuration IO1 x The Voltage module consists of an 11bit resistor string - DAC with buffered output and a subsequent inverting amplifier with class AB rail-to-rail OPAMP. The two feedback nets are connected to the Pins FBN and FBP. This structure offers wide flexibility for the output configuration, for example voltage output and 4 mA to 20 mA current loop output. To short circuit the analog output against VSS or VDDA does not damage the ZMD31050. The PWM module provides pulse streams with signal dependent duty cycle. The PWM - frequency depends on resolution and clock divider. The maximum resolution is 12 bit, the maximum PWM - frequency is 4 kHz (9 bit). If both, second PWM and SPI protocol are activated, the output pin IO1 is shared between the PWM output and the SPI_SDO output of the serial interface (Interface communication interrupts the PWM output). 1.5.2. Comparator Module (ALARM Output) The comparator module consists of two comparator channels connectable to IO1 and IO2 respectively. Each of them can be independently programmed referring to the parameters threshold, hysteresis, switching direction and on/off - delay, additional a window comparator mode is available. 1.5.3. Serial Digital Interface The ZMD31050 includes a serial digital interface which is able to communicate in three different communication protocols - I2CTM, SPITM and ZACwireTM (one wire communication). In the SPI mode the pin IO2 operates as slave select input, the pin IO1 as data output. Initializing Communication After power-on the interface is for about 20ms (start window) in the state ZACwire. During the start window it is possible to communicate via the one wire interface (pin OUT). Detecting a proper request inside the start window the interface stays in the state ZACwire. This state can be left by certain commands or a new power-on. If no request happens during the start window then the serial interface switches to I2C or SPI mode (depending on EEPROM settings) and the OUT pin is used as analog output or as PWM output (also depending on EEPROM settings. The start window can generally be disabled (or enabled) by a special EEPROM setting. For detailed description of the serial interfaces see "ZMD31050 Functional Description". Copyright (c) 2005, ZMD AG, Rev. 0.95, 2005-09-16 10/20 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The Information furnished in this publication is preliminary and subject to changes without notice. ZMD31050 Advanced Differential Sensor Signal Conditioner Datasheet 1.6 Voltage Regulator PRELIMINARY For ratiometric applications 3V to 5V (10%) the external supply voltage can be used for sensor element biasing. If an absolute analog output is desired then the internal voltage regulator with external power regulation element (FET) can be used. It is bandgap reference based and designed for an external supply range VSUPP = (7 to 40) VDC. With the voltage regulator the internal supply and sensor bridge voltage can be varied between 3V and 5V. 1.7 Watchdog and Error Detection The ZMD31050 detects various possible errors. A detected error is signalized by changing in a diagnostic mode. In this case the analog output is set to High or Low (maximum or minimum possible output value) and the output registers of the digital serial interface are set to a significant error code. A watchdog oversees the continuous working of the CMC and the running measurement loop. A check of the sensor bridge for broken wires is done permanently by two comparators watching the input voltage of each input [(VSSA + 0.5V) to (VDDA - 0.5V)]. Add on the common mode voltage of the sensor is watched permanently (sensor aging). Different functions and blocks in digital part are watched like RAM-, ROM,- EEPROM- and Register content continuously, the document "ZMD31050 Functional Description" contains in chapter 1.3.4 a detailed description of all watched blocks and methods of messaging of errors. Copyright (c) 2005, ZMD AG, Rev. 0.95, 2005-09-16 11/20 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The Information furnished in this publication is preliminary and subject to changes without notice. ZMD31050 Advanced Differential Sensor Signal Conditioner Datasheet PRELIMINARY 2. Application Circuit Examples 100 n 390 VOUT 0...10V 2,2 k ZMD 31050 IN3 ZMD 31050 VDC 12...40V 100 n 1k 2,0 k Example 1 Typical ratiometric measurement with voltage output, temperature compensation via external diode, internal VDD regulator and active sensor connection check (bridge must not be at VDDA) Example 2 0V to 10V output configuration, supply regulator (external JFET), temperature compensation via internal diode and bridge in voltage mode PWM-Out ZMD 31050 ZMD 31050 Example 3 Absolute voltage output, supply regulator (external JFET), constant current excitation of the sensor bridge, temperature compensation by bridge voltage drop measurement, internal VDD regulator without ext. capacitor Example 4 Ratiometric bridge differential signal measurement, 3-wire connection for end of line calibration at pin OUT (ZACwireTM), additional temperature measurement with external thermistor and PWM-output at pin IO1 Hint: It is possible to combine or split connectivity of different application examples. For VDD generation ZMD recommends to use internal supply voltage regulator with external capacitor (refer example 1). Copyright (c) 2005, ZMD AG, Rev. 0.95, 2005-09-16 12/20 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The Information furnished in this publication is preliminary and subject to changes without notice. ZMD31050 Advanced Differential Sensor Signal Conditioner Datasheet PRELIMINARY 3. ESD/Latch-Up-Protection All pins have an ESD Protection of >2000V (except the pins INN, INP and FBP with > 1200V) and a Latch-up protection of 100mA or of +8V/ -4V (to VSS/VSSA) - refer chapter 4 for details and restrictions. ESD Protection referred to the human body model is tested with devices in SSOP16 packages during product qualification. The ESD test follows the human body model with 1.5kOhm/100pF based on MIL 883, Method 3015.7. 4. Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Pin Configuration and Package Name VDDA IN3 VGATE IO1 IO2 SCL SDA VDD FBN OUT FBP IR_TEMP VBR VINP VSS VINN Description Positive analog supply voltage Resistive temp sensor IN & external clock IN Gate voltage for external regulator FET SPI data out & ALARM1 & PWM1 Output SPI chip select & ALARM2 IC clock & SPI clock Data IO for IC & data IN for SPI Positive digital supply voltage Negative feedback connection output stage Analog output & PWM2 Output & one wire interface i/o Positive feedback connection output stage Current source resistor i/o & temp. diode in Bridge top sensing in bridge current out Positive input sensor bridge Negative supply voltage Negative input sensor bridge Remarks Supply Analog IN Analog OUT Digital IO Digital IO Latch-Up related Application Circuit Restrictions and/or Remarks free accessible (latch-up related) only connection to external FET free accessibility free accessibility Digital IN, pull-up free accessibility Digital IO, pull-up free accessibility Supply Analog IO Analog OUT & dig. IO Analog IO Analog IO Analog IO Analog IN Ground Analog IN free accessibility only short to VDDA or capacitor to VSS allowed, otherwise no application access free accessibility free accessibility free accessibility circuitry secures potential inside of VSS-VDDA range, otherwise no application access only short to VDDA or connection to sensor bridge, otherwise no application access free accessibility Table 6: Pin configuration The standard package of the ZMD31050 is a SSOP16 (5.3mm body width) with lead-pitch 0.65mm: Pin-Nr 9 10 11 12 13 14 15 16 Pin-Name FBN OUT FBP IR_TEMP VBR VINP VSS VINN Pin-Name VDD SDA SCL IO2 IO1 VGATE IN3 VDDA Pin-Nr 8 7 6 5 4 3 2 1 Copyright (c) 2005, ZMD AG, Rev. 0.95, 2005-09-16 13/20 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The Information furnished in this publication is preliminary and subject to changes without notice. 16 1 ZMD U23456 abcd xxxx YYWW ZMD31050 Advanced Differential Sensor Signal Conditioner Datasheet PRELIMINARY 5. 5.1 No. 5.1.1 5.1.2 5.1.3 5.1.4 5.1.5 5.2 No. 5.2.1 5.2.2 5.2.3 5.2.4 5.2.5 5.2.6 5.2.7 5.2.8 5.2.9 IC Characteristics Absolute Maximum Ratings Parameter Digital Supply Voltage Analog Supply Voltage Voltage at all analog and digital I/O - Pins Voltage at Pin FBP Storage temperature Operating Conditions Parameter Ambient temperature Ambient temperature advanced performance Ambient temperature EEPROM programming EEPROM programming cycles Data retention (EEPROM) Analog Supply Voltage Analog Supply Voltage advanced performance Digital Supply Voltage External Supply Voltage VDDA VDDAADV VDD VSUPP VIN_CM 2.7 4.5 2.7 VDDA + 2V 0.21 Symbol TAMB TAMB_ADV TAMB_EEP min -40 -25 -25 typ max 125 85 85 100 15 5.5 5.5 1.05 40 0.76 a V DC V DC avg. temp < 85grd ratiometric mode ratiometric mode Unit C C C Symbol VDDAMR VDDAAMR VA_I/O, VD_I/O VFBP_AMR TSTG min -0.3 -0.3 -0.3 -1.2 -45 typ max 6.5 6.5 VDDA +0.3 VDDA +0.3 150 Unit V DC V DC V DC V DC C (Voltages related to VSS) Conditions Conditions to VSS to VSS Exception s. 5.1.4 4 mA to 20mA - Interface VDDA external powered V DC V DC voltage regulator mode with ext. JFET 5.2.10 Common mode input range VADC_REF depends on gain adjustment refer chapter 1.3.1 Copyright (c) 2005, ZMD AG, Rev. 0.95, 2005-09-16 14/20 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The Information furnished in this publication is preliminary and subject to changes without notice. ZMD31050 Advanced Differential Sensor Signal Conditioner Datasheet No. Parameter Symbol VIN_FBP RBR min -1 3.0 5.0 1 PRELIMINARY typ max VDDA 25.0 25.0 Unit Conditions V DC k k RBR 100 100 470 470 50 2 10 nF nF nF k nF full temperature range 4mA to 20mA - Interface leads to IBR = VDDA / (16*RBR_REF) between VDDA and VSS, external between VDD and VSS, external Output Voltage mode Output Voltage mode summarized to all potentials 5.2.11 Input Voltage Pin FBP 5.2.12 Sensor Bridge Resistance 5.2.13 Reference Resistor for Bridge Current Source * 5.2.14 Stabilization Capacitor * 5.2.15 Optional Stabilization Capacitor * 5.2.16 Maximum allowed load capacitance at OUT3 5.2.17 Minimum allowed load resistance 5.2.18 Maximum allowed load capacitance at VGATE 5.3 No. 5.3.1. 5.3.2 Build In Characteristics Parameter Selectable Input Span, Pressure Measurement Analog Offset Compensation Range (6 Bit setting) A/D Resolution D/A Resolution PWM - Resolution Reference current for external temperature diodes Sensitivity internal temperature diode RBR_REF CVDDA CVDD CL_OUT RL_OUT CL_VGATE 0.07 50 0 2 Symbol VIN_SP min 1 -20 -25 -31 9 typ max 275 20 25 31 15 Unit Conditions mV/V 4 Bit setting s. 3.3.1 count ADJREF:BCUR>3 ADJREF:BCUR=7 3 Bit setting @ analogue output 5.3.3 5.3.4 5.3.5 5.3.6 rADC rDAC rPWM ITS Bit Bit 11 9 8 18 12 40 Bit A 5.3.7 STT_SI 2800 3200 3600 ppm Raw values - without f.s. /K conditioning 1 2 3 no measurement in mass production, parameter is guarantied by design and/or quality observation no limitations with an external connection between VDDA and VBR lower stabilization capacitors can increase noise level at the output if used, consider special requirements of ZACwireTM single wire interface stated in "Functional Description" chapter 4.3 Copyright (c) 2005, ZMD AG, Rev. 0.95, 2005-09-16 15/20 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The Information furnished in this publication is preliminary and subject to changes without notice. ZMD31050 Advanced Differential Sensor Signal Conditioner Datasheet 5.3.8 Cycle Rate versus A/D-Resolution (linear related to master clock frequency1 - values calculated at exact 2 MHz ) ADC Order Resolution OADC rADC Bit 1 9 10 11 12 13 14 15 2 11 12 13 14 15 5.3.9 PWM Frequency * PWM Freq./Hz at 2 MHz Clock1 Clock Divider 1 0,5 0,25 0,125 3906 1953 977 488 1953 977 488 244 977 488 244 122 488 244 122 61 PWM Freq./Hz at 2.25 MHz Clock2 Clock Divider 1 0,5 0,25 0,125 4395 2197 1099 549 2197 1099 549 275 1099 549 275 137 549 275 137 69 PRELIMINARY Conversion Cycle fCYC fCLK=2MHz fCLK=2.25MHz Hz Hz 1302 1465 781 879 434 488 230 259 115 129 59 67 30 34 3906 4395 3906 4395 1953 2197 1953 2197 977 1099 PWM Resolution rPWM [Bit] 9 10 11 12 1 2 no measurement in mass production, parameter is guarantied by design and/or quality observation Internal RC - Oscillator: coarse adjustment to1, 2 and 4 MHz, fine tuning +/- 25% , external clock is also possible Internal RC - Oscillator: coarse adjustment to1.125, 2.25 and 4.5 MHz, fine tuning +/- 25% , external clock is also possible Copyright (c) 2005, ZMD AG, Rev. 0.95, 2005-09-16 16/20 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The Information furnished in this publication is preliminary and subject to changes without notice. ZMD31050 Advanced Differential Sensor Signal Conditioner Datasheet 5.4 No. Electrical Parameters Parameter Symbol min typ max Unit mA PRELIMINARY (Voltages related to VSS) Conditions without bridge current and without load current, fCLK 2.25MHz without bridge current, fCLK 1.2MHz, BiasAdjustment 1 5.4.1.1 Supply current 5.4.1 Supply / Regulation ISUPP 2.5 4 5.4.1.2 Supply current for current loop 5.4.1.2 Temperature Coeff. Voltage Reference * ISUPP_CL 2.0 2.75 TCREF -200 +/- 50 200 ppm/K 5.4.2 Analog Front End 5.4.2.1 Parasitic differential input offset current IIN_OFF -2 to 10 2 to 10 nA temp. range 5.2.2., TADV 5.4.3 DAC & Analog Output (Pin OUT) 5.4.3.1 Output signal range 5.4.3.2 Output slew rate * VOUT_SR SROUT IOUT_max VOUT_ADR 0.025 0.1 5 0 10 0.975 VDDA Voltage mode, assuming maximum load of 2k V/s 20 1 mA Voltage mode, CL<20nF @ VOUT_SR: 5.4.2.1 5.4.3.3 Short circuit current * 5.4.3.4 addressable output signal range * VDDA 2048 steps 5.4.4 PWM Output (Pin OUT, IO1) 5.4.4.1 PWM high voltage 5.4.4.2 PWM low voltage 5.4.4.3 PWM output slew rate* VPWM_H VPWM_L SRPWM 15 0.9 0.1 VDDA VDDA V/s RL > 10 k RL > 10 k CL < 1nF 5.4.5 Temperature Sensors (Pin IR_TEMP) 5.4.5.1 Sensitivity external diode / resistor meas. STTS_E 75 210 V / LSB at rADC = 13 Bit 5.4.6 Digital Outputs (IO1, IO2, OUT in digital mode) 5.4.6.1 Output-High-Level 5.4.6.2 Output-Low-Level 5.4.6.3 Output Current VDOUT_H VDOUT_L IDOUT 0.9 0.1 4 VDDA RL > 1 k VDDA RL > 1 k mA no measurement in mass production, parameter is guarantied by design and/or quality observation Copyright (c) 2005, ZMD AG, Rev. 0.95, 2005-09-16 17/20 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The Information furnished in this publication is preliminary and subject to changes without notice. ZMD31050 Advanced Differential Sensor Signal Conditioner Datasheet No. Parameter Symbol min typ max Unit Conditions PRELIMINARY 5.4.7 System Response 5.4.7.1 Startup time 1 tSTA 2 5 ms Power up to first measure result at output, OWI - start window disabled refer chapter 1.3.4 for fCON 5.4.7.2 Response time 5.4.7.3 Overall accuracy (deviation from ideal line including INL, gain and offset errors) 5.4.7.4 Peak-to-PeakNoise@output * 5.4.7.5 Ratiometricity Error 5.5 No. Interface Characteristics Parameter tRESP ACOUT 2/fCON 3/fCON 0.1 0.25 % % mV TADV, VADV (-25 to +85)C, (4.5 to 5.5)V For decreased current consumption ADJREF:BCUR>3 VOUT_NS REOUT_5 REOUT_3 5 500 1000 shorted inputs, bandwidth 2kHz ppm 4.5 - 5.0V & 5.0 - 5.5V ppm 2.7 - 3.0V & 3.0 - 3.3V Symbol min typ max Unit Conditions 5.5.1 Multiport Serial Interfaces (I2C, SPI) 5.5.1.1 Input-High-Level 5.5.1.2 Input-Low-Level 5.5.1.3 Output-Low-Level 5.5.1.4 load capacitance @ SDA 5.5.1.5 Clock frequency SCL 5.5.1.6 Pull-up Resistor VI2C_IN_H VI2C_IN_L VI2C_OUT_L CSDA fSCL RI2C_PU 500 0.7 0 1 0.3 0.1 400 400 VDDA VDDA VDDA pF kHz 0.05 0.08 0.2 0.75 ROWI_PU tOWI_BIT / ROWI_PU VDDA VDDA 20s < tOWI_BIT < 100s 5.5.2 One Wire Serial Interface (ZACwireTM) 5.5.2.1 Pull-up resistance master 5.5.2.2 OWI line resistance 5.5.2.3 OWI load capacitance 5.5.2.4 Voltage level Low 5.5.2.5 Voltage level High 1 ROWI_PU ROWI_LINE COWI_LOA D 330 VOWI_L VOWI_H no measurement in mass production, parameter is guarantied by design and/or quality observation Depends on resolution and configuration - start routine begins approximately 0.8ms after power on Copyright (c) 2005, ZMD AG, Rev. 0.95, 2005-09-16 18/20 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The Information furnished in this publication is preliminary and subject to changes without notice. ZMD31050 Advanced Differential Sensor Signal Conditioner Datasheet PRELIMINARY 6. Test Refer "ZMD31050 Test Flow Description" for a detailed test flow and test conditions. 7. Reliability A reliability investigation according to the in-house non-automotive standard will be performed. 8. Customization For high-volume applications, which require an up- or downgraded functionality compared to the ZM31050, ZMD can customize the circuit design by adding or removing certain functional blocks. For it ZMD has a considerable library of sensor-dedicated circuitry blocks. Thus ZMD can provide a custom solution quickly. Please contact ZMD for further information. 9. * * * * * * Related Documents ZMD31050 ZMD31050 ZMD31050 ZMD31050 ZMD31050 ZMD31050 Feature Sheet Functional Description Evaluation Kit Description Development Status Report (including parts identification table) Test Flow Description Application Notes Copyright (c) 2005, ZMD AG, Rev. 0.95, 2005-09-16 19/20 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The Information furnished in this publication is preliminary and subject to changes without notice. ZMD31050 Advanced Differential Sensor Signal Conditioner Datasheet NOTES: PRELIMINARY This information applies to a product under development. Its characteristics and specifications are subject to change without notice. ZMD assumes no obligation regarding future manufacture unless otherwise agreed in writing. The information furnished hereby is believed to be correct and accurate. However, ZMD shall not be liable to any customer, licensee or any other third party for any damages in connection with or arising out of the furnishing, performance or use of this technical data. No obligation or liability to any customer, licensee or any other third party shall result from ZMD's rendering of technical or other services. For further information: ZMD AG Grenzstrasse 28 01109 Dresden, Germany Phone +49 (0)351-8822-366 Fax +49 (0)351-8822-337 sales@zmd.de www.zmd.biz ZMD America, Inc. 201 Old Country Road, Suite 204 Melville, NY 11747, USA Phone +01 (631) 549-2666 Fax +01 (631) 549-2882 sales@zmda.com www.zmd.biz ZMD America, Inc. 15373 Innovation Drive, Suite 110 San Diego, CA 92128, USA Phone +01 (858) 674-8070 Fax +01 (858) 674-8071 sales@zmda.com www.zmd.biz Copyright (c) 2005, ZMD AG, Rev. 0.95, 2005-09-16 20/20 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The Information furnished in this publication is preliminary and subject to changes without notice. |
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